1. Field of the Invention
The present invention is related to a switching voltage regulator, and more particularly, to a switching voltage regulator capable of fixing a floating threshold of a load current.
2. Description of the Prior Art
In order to prevent disturbances induced by a voltage source from influencing an electronic device, circuit designers usually install voltage regulators between the voltage source and the electronic device, to stabilize a voltage supplied by the voltage source, so as to output the voltage at a level conforming to a designated level for the electronic device. In general, voltage regulators can be divided into two categories: linear and switching. A linear regulator stabilizes its output voltage by controlling a current between a voltage source and a load. Accordingly, in a switching regulator, a current between a voltage source and a load is not continuous but composed by discrete current impulses. To generate the current impulses, a switch, such as a power transistor, is installed between the voltage source and the load of the switching regulator. As a result, the switching regulator can convert the current impulses into a stable load current through inductor components embedded at an output end of the switching regulator.
Please refer to FIG. 1, which is a schematic diagram of a switching regulator 10 of the prior art. The switching regulator 10 is utilized for converting an input voltage VIN into a stable output voltage VOUT sent to a load RL. The switching regulator 10 mainly includes an input end 100, an output end 102, a switch module 110, an output module 120, a first comparator 130, a second comparator 132, a third comparator 134, an OR gate 135, an oscillator 136, a set-reset (SR) flip-flop 138, a transconductance amplifier 140, a compensation current source 142, a filter module 150 and a feedback module 160. The input end 100 is utilized for receiving the input voltage VIN. The transconductance amplifier 140 detects a variance of a voltage difference between two ends of a sensing resistor RSEN, to generate a sensing current IS. The compensation current source 142 is utilized for providing a compensation current ISC. A sum of the sensing current IS and the compensation current ISC can be regarded as a sawtooth wave current IRAMP, which generates a sawtooth wave signal VRAMP at a “+” input end of the third comparator 134. The feedback module 160 divides the output voltage VOUT to generate the feedback signal VFB. The first comparator 130 compares the feedback signal VFB and a reference voltage VREF to generate a first comparison result VCMP1. The filter module 150 then filters the first comparison result VCMP1. The third comparator 134 compares the sawtooth wave signal VRAMP and the first comparator result VCMP1, to generate a third comparison result VCMP3. In addition, the second comparator 132 compares a voltage VIN-VTH with a voltage of a “−” end of the transconductance amplifier 140, to generate a second comparison result VCMP2. The OR gate 135 performs a logic OR operation on the second comparison result VCMP2 and the third comparison result VCMP3 to generate a logic result LOG. The oscillator 136 is utilized for providing an oscillation signal VOSC. The SR flip-flop 138 sets a switching signal SW to be a high potential level according to the oscillation signal VOSC, and resets the switching signal SW to be a low potential level according to the logic result LOG. The switch module 110 includes a power transistor 112 and a diode 114, such that the switching regulator 10 can determine whether the input end 100 is electrically connected to the output end 102 according to the switching signal SW. Finally, the output module 120 is utilized for generating the output voltage VOUT, and includes an output inductor 122 and an output capacitor 124.
In short, the switching regulator 10 operates in an “ON” period or an “OFF” period. In the “ON” period, the oscillation signal VOSC is at a high voltage level, and can set the switching signal SW to be the high potential level, so as to enable the power transistor 112. In such a situation, an input current Ii flows from the input end 100 via the power transistor 112 to the output module 120, to generate the output voltage VOUT. Inversely, in the “OFF” period, the SR flip-flop is reset since the input current Ii exceeds a default threshold or the output voltage VOUT exceeds a default threshold, such that the power transistor 112 is disabled and the diode 110 is forward biased. As a result, via the diode 110, the output inductor 122 can draw a load current IRL required by the load RL from a ground GND.
Note that, the switching regulator 10 has a natural shortcoming of being unstable when a duty cycle of the power transistor 112 exceeds 50%. Thus, other than traditional feedback schemes, the switching regulator 10 implements a slope compensation scheme by adding the compensation current source 142. Moreover, the switching regulator 10 further includes the second comparator 132 to achieve a constant load current threshold. However, since the input voltage VIN is a high voltage, the second comparator 132 must be capable of bearing high voltages. To do so, the second comparator 132 has to be implemented by larger circuit layout area and operate at a slower speed as compared to other components in the switching regulator 10, leading to a higher manufacturing cost.
Please continue to refer to FIG. 2, which is a schematic diagram of another switching regulator 20 of the prior art. The switching regulator 20 is similar to the switching regulator 10 except that a “+” input end of the second comparator 132 is coupled to the “+” input end of the third comparator 134, and a “−” input end of the second comparator 132 is coupled to a constant voltage signal VCPS in the switching regulator 20. As a result, the second comparator 132 no longer has to bear high voltages and can be implemented with a simpler architecture, to reduce the manufacturing cost and enhance operation speed.
However, in the switching regulator 20, when the load current IRL reaches a default threshold, VCPS=VRAMP, i.e. Ifix·R1=(ISC+IS)·R2. If the sensing current IS is divided into a time-variant component IS(t) and a constant component IS_fix (IS=IS_fix+IS(t)), and the compensation current ISC component is divided into a time-variant component ISC(t) and a constant component ISC_fix(ISC=/ISC_fix+ISC(t)), the time variant component of the sensing current IS(t) can be represented as:
                              IS          ⁡                      (            t            )                          =                              Ifix            ·                          (                                                R                  ⁢                                                                          ⁢                  1                                                  R                  ⁢                                                                          ⁢                  2                                            )                                -          ISC_fix          -          IS_fix          -                                    ISC              ⁡                              (                t                )                                      .                                              (                  Eq          .                                          ⁢          1                )            
Moreover, based upon characteristics of the transconductance amplifier 140, the time-variant component of the sensing current IS (t) further can be represented as:IS(t)=gm·RSEN·Ii(t)=gm·RSEN·IRL(t),  (Eq. 2)where gm represents a transconductance gain of the transconductance amplifier 140, Ii(t) represents a time-variant component of the input current Ii, and IRL(t) represents a time-variant component of the load current IRL. Thus, if Eq. 1 is substituted into Eq. 2, the time-variant component of load current IRL(t) can be represented as:
                              IRL          ⁡                      (            t            )                          =                                            1                              gm                ·                RSEN                                      ⁡                          [                                                Ifix                  ·                                                            R                      ⁢                                                                                          ⁢                      1                                                              R                      ⁢                                                                                          ⁢                      2                                                                      -                ISC_fix                -                IS_fix                            ]                                -                                    1                              gm                ·                RSEN                                      ·                                          ISC                ⁡                                  (                  t                  )                                            .                                                          (                  Eq          .                                          ⁢          3                )            
In Eq. 3, the threshold of the load current IRL is not a constant but varies with the compensation current ISC. More specifically, the greater the compensation current ISC, the greater the chance that the threshold of the load current is lower than the designated threshold.
Therefore, how to implement the switching regulator without sacrificing stability and increasing manufacturing costs has been a major focus of the industry.